TCAD analysis of SiGe channel FinFET devices

SiGe FinFET devices have many unique device elements which differ from conventional Si FinFET devices. Here we discuss their threshold voltage sensitivity, stress profiles, long channel mobility behavior, and the presence of traps at the gate oxide interface. In order to achieve a well-performing SiGe FinFET device it is important to understand the physical nature of these elements and incorporate them in a well-calibrated TCAD deck. In this paper, we examine each element with experimental data and calibrate the TCAD deck by introducing new boundary conditions, implementing a new Dit extraction method, and adjusting the material parameters. Special consideration is given to the treatment of interface traps since the readout of the trap density with the conductance method used in experiments does not represent the actual trap distribution. Finally, we review the short channel transistor performance and provide guidelines on how to achieve a high-performing device.