An effective algorithm for gate-level power-delay tradeoff using two voltages

We present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the timing slack distribution and power/delay model within the circuit. The power reduction is then translated into the Maximal-Weighted-Independent-Set (MWIS) problem. We develop an effective power optimization algorithm based on MWIS. To reduce the possible power penalty of level converters (LCs) at the interface of two supply voltages, we use a "constrained" F-M algorithm to minimize the number of LCs. Experimental results show that the total power saving up to 35% (average of about 19%) is achieved without degrading the circuit performance. The power-delay tradeoff is provided by specifying different timing constraints for power optimization.