Design of High Speed Lifting Based DWT Using 9/7 Wavelet Transform for Image Compression

Design of Lifting based DWT architecture is proposed in this paper for high speed processing so that it may be realized as an FPGA or as an ASIC. The proposed architecture includes Line Buffers, PIPO and Lifting Block. This architecture works in non separable fashion using a lifting scheme and computes 2D-DWT at different resolution levels. The lifting scheme offers the fastest possible implementation of the DWT. The architecture has been coded using RTL Verilog and synthesized using Xilinx 14.4, targeted on Spartan 6- XC6SLX4L FPGA. A regular systolic structure has been proposed in this architecture with simple control flow for data extraction and small embedded buffers. The maximum frequency of operation reported by Place & Route tool is 254 MHz for 3-Level 2D-DWT. The FPGA mapping compares favourably with another FPGA implementation.