Enhanced injection in n/sup ++/-poly/SiO/sub x//SiO/sub 2//p-sub MOS capacitors for low-voltage nonvolatile memory applications: experiment

In this paper, n/sup ++/-poly/SiO/sub x//SiO/sub 2//p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiO/sub x/ films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiO/sub x/ film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n/sup ++/-poly/SiO/sub x//SiO/sub 2//p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiO/sub x/ films is proposed. In SiO/sub x/ films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiO/sub x//SiO/sub 2/ interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiO/sub x/ films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap.