Implementation and designing of FIR filters using kaiser window for de-noising of electrocardiogram signals on FPGA

The proposed work deals with design and implementation of Kaiser window based FIR filters for de-noising ECG Signals. This work considered serial cascading of three filters – Low pass filter for unwanted high frequency components, High pass filter for unwanted low frequency components and Band stop filters for unwanted particular frequencies of 50Hz/60Hz. This work lead in a direction for minimization of the artefacts in Electrocardiogram signals using Kaiser Window based FIR digital filter. Further implementation of filters on Reconfigurable architectures i.e. SPARTAN ADSPxc3sd1800a-4cs484–4 & VIRTEX 5vlx50tff1136–3 FPGA Boards lead to accomplish the low power, less area, low cost and high speed. Results are realized on MATLAB software and Xilinx ISE software.