Design and implementation of efficient IIR LMS adaptive filter with improved performance

The evolution of multi-feature portable devices with high speed processors and with drastic growth in component density turns the designer attention towards power aware design schemes. In low power VLSI designs an adaptive filter can obtain a reduction in terms of area and power consumption. A system with a linear transfer function controlled by variable parameters and a means to adjust those parameters according to an optimization algorithm is called adaptive filter. The Least Mean Square (LMS) filter is one of adaptive filters type which is used commonly, because of its simplicity and also because of its satisfactory convergence performance. The current IIR adaptive filter uses LMS to reduce area-delay product and energy-delay product. To reduce this delay one can implement filter in pipelined structure. Shift-add tree efficiently minimizes the critical path and silicon area without increasing the number of adaptation delays. The structure of IIR adaptive filter designing is done by using two main blocks: IIR block and new coefficients block (weights block). Weights block consists of series of partial product generators and shift/add tree. Partial product generators has 2 to 3 decoders and AND/OR cells. Weights block performs multiply accumulate operations. Filter block depends upon on the new filter coefficients obtaining from weights block. The proposed filter is designed in MATLAB (2013a) for its performance characteristics and its constraints are verified using XILINX (verl4.7) implemented on FPGA.