A New FPGA-Based Segmented Delay-Line DPWM With Compensation for Critical Path Delays

The duty cycle in digital pulse width modulation (DPWM) whose time resolution is as high as hundreds of picosecond will be increased since the propagation delays of internal logics and interconnects are superimposed on the on-time. The duty-cycle-increment phenomenon affects the regulation performance of converters, especially when the delays are the same magnitude level as switching period. In this paper, a compensation method based on tool command language commands is used to offset the propagation delays. Furthermore, the DPWM applies a counter, phase locked loop, and carry chain to constitute segmented delay-line, while it maintains a wide duty cycle range and a high time resolution. This DPWM is implemented by a low-cost field-programmable gate array Cyclone IV. It achieves a good linearity where R2 is 0.9949 for an 11-bit, 9.375 MHz switching frequency DPWM. The duty cycle range is from 1.52% to 97.81%. Meanwhile, the time resolution and average duty difference are 53 ps and 3.08%, respectively.