A wide-range low-jitter fully integrated programmable frequency synthesizer building block in a 2.5 V/0.25 /spl mu/m CMOS process

This paper describes the design of a wide-range programmable frequency synthesizer building block for graphics-application ASICs. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as zero location in order to handle the wide range of divider values. The synthesizer input frequency range is 2.8125 MHz to 200 MHz, while the output frequency is programmable (via dividers) in the range 5.46875 MHz to 350 MHz. A fully integrated, differential structure results in low jitter. The use of BIST (Built In Self Test) for facilitating production testing is also discussed.