ESD protection design and verification in a 0.35-/spl mu/m CMOS ASIC library

In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-/spl mu/m silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-/spl mu/m CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-/spl mu/m CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.