A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations

This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadratic programming (QP) problem is introduced. To evaluate the reliability, a quadratic cost function is introduced as the Euclidean distance between a specified ideal schedule and a feasible clock schedule. Unlike previous work, the algorithms presented here can be employed to obtain specified target values of the clock delays/skews within a circuit, such as for example, the clock delays/skews for the I/O registers. An efficient mathematical algorithm is derived for the solution of the QP problem with O(r/sup 3/) run time complexity and O(r/sup 2/) storage complexity, where r is the number of registers in the circuit. The algorithm is implemented as a C++ program and demonstrated on the ISCAS'89 suite of benchmark circuits as well as on a number of industrial circuits. The research described here yields additional insights into the correlation between circuit structure and circuit timing by characterizing the degree to which specific signal paths limit the overall performance and reliability of a circuit. This information is therefore applicable to logic and architectural synthesis.