Efficient modeling techniques for IR drop analysis in ASIC designs

In this paper, we propose efficient modeling techniques for analyzing power distribution in deep submicron (DSM) ASIC designs. VCCS (Voltage Controlled Current Source) and equivalent conductance modeling techniques are the key concepts in our approach, which provide the same analysis results as the original resistive network with two orders of magnitude speedup. In addition, soft-macro power consumption modeling is proposed to enable the analysis at the floorplan stage. Experimental results show that the power distribution analysis based on the proposed modeling techniques at the floorplan stage yields less than 5% error compared to the post-layout power analysis.