Smart transducer architectural organisation based on standard IEEE P1451

A distribution of intelligence within complex measuring-information and control systems can result in significant improvements to performance and functionality of that system, whilst also, providing facilities that are difficult or impossible to attain using conventional techniques. Microelectronics today makes it possible to execute information processing necessary to control, monitoring and communicating of processes by installing smart transducers. An approach to design the overall system architecture and functions of a smart transducer interface architecture according to the IEEE P1451 standard, is discussed in this paper. A standard model of a smart transducer interface decomposition, with the aim to generate a functional structure at architectural level for each building block, is employed. The described approach is appropriate for Si monolithic implementation as a linear processing chain of several ASIC chips.