Case study of inter-metal dielectric cu residue induced early life leakage increase

This is a case study of an early failure analysis on a chip fabricated on the 40nm technology node. A large leakage current was observed in the high voltage (HV) supply after the chip was stressed as a part of an early failure rate (EFR) test. Electrical failure analysis (EFA) using Backside Emission spectroscopy [1] and Optical Beam Induced Resistance Change (OBIRcH) [2] showed the existence of hotspots, but no silicon damage was observed after de-processing. OBIRCH also highlighted a long section of an interconnect, but was not useful to localize the defect. Circuit analysis, including metal net tracing indicated a possible short between a via landing pad and a minimum spaced adjacent metal line as the most likely source of the problem. This would bias the gate of a nominally off transistor leading to a leakage path. Physical failure analysis (PFA) revealed traces of Cu in the Inter-metal dielectric (IMD) between the via and adjacent metal line as the source of the leakage. Cu residue was also observed in an unstressed die. The root cause was determined to be a combination of Via etch induced damage to the underlying metal sidewall and non-optimized Cu CMP at the lower levels of metal that resulted in a high dielectric recess. Appropriate process optimization actions were then undertaken to solve the issue.