Stress analysis on ultra-thin ground CMOS-MEMS wafers via micro-Raman spectroscopy

A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35~275 μm by means of a micro-Raman technique. We found that the grinding process used did not add a significantly stress on the thinned MEMS wafer. In contrast, a severe compressive stress with a wide range of stress distribution was found on the thinned CMOS wafer.