ESD protection design for VBO-based high-speed multimedia interface chip

Traditional ESD protection program cannot meet requirements of higher ESD protection grade and parasitic parameter of protection devices when using V-by-One high-speed interface chip. This paper proposes an effective ESD protection program by way of reverse analysis and design of a VBO-based high-speed interface chip failure case. The program introduces a new SCR structure replacing the original diode series structure. The new structure is featured as small back delay, with leakage current to the nano level. 43.3mA/um and 34.8mA.um are achieved when 28nm process and 40nm process are applied separately. What's more, by improving the structure parameters, the new program also make the Windows meet the requirements of VBO-based high-speed interface chip.