Design and simulation of physical layer blocks of ZigBee transmitter

On account of increasing use and demand of Internet of Things, and subsequently the need for developing Wireless Sensor Networks, technologies like ZigBee are becoming more and more important. Especially, the low power consumption and low cost provided by ZigBee enables longer life, smaller batteries and wide acceptance. Hence it is best suited for IoT applications like Smart homes, intelligent transportation systems, health monitoring systems and many more. This paper proposes an architectural design of the Zigbee Transmitter through Verilog HDL. As the transmitter is an integration of various blocks, so each block is simulated and their individual results are presented in this paper. For efficient hardware implementation on FPGA/ASIC, optimization of the design is of paramount importance. This can be done by architectural coding of the design. Hence, the architecture has been simulated and the post route simulation output has been presented in this paper.