Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing

In this paper, dynamic algorithm transformations (DATs) for designing low-power reconfigurable signal-processing systems are presented. These transformations minimize energy dissipation while maintaining a specified level of mean squared error or signal-to-noise ratio. This is achieved by modeling the nonstationarities in the input as temporal/spatial transitions between states in the input state-space. The reconfigurable hardware fabric is characterized by its configuration state-space. The configurable parameters are taken to be the filter taps, coefficient and data precisions, and supply voltage V/sub dd/. An energy-optimal reconfiguration strategy is derived as a mapping from the input to the configuration state-space. In this strategy, taps are powered down starting with the tap with the smallest value [w/sub k//sup 2///spl Sigma//sub m/(w/sub k/)] (where w/sub k/ and /spl Sigma//sub m/(w/sub k/) are, respectively, the adders, redundant-to-binary conversion, tree adders, coefficient and energy dissipation of the kth tap). Optimal values for precision and supply voltage V/sub dd/ are subsequently computed from the roundoff error and critical path delay requirements, respectively. The DAT-based adaptive filter is employed as a near-end crosstalk (NEXT) canceller in a 155.52-Mb/s asynchronous transfer mode-local area network transceiver over category-3 wiring. Simulation results indicate that the energy savings range from -2% to 87% as the cable length varies from 110 to 40 m, respectively, with an average saving of 69%. An average saving of 62% is achieved for the case where the supply voltage V/sub dd/ is kept fixed.