Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs

The importance of efficient area and timing estimation techniques is well-established in high-level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based solely on the gate and/or literal count. Those models are not accurate enough to allow effective design space exploration since the effects of interconnect can indeed dominate the final design cost. The situation becomes even worse when the design is targeted to field-programmable gate array (FPGA) technologies since the wire delay may contribute up to 60% of the overall design delay. In this paper, we present an approach of estimating area and timing for lookup-table-based FPGAs that takes into account not only gate area and delay, but also the wiring effects. We select the Xilinx XC4000 series as our main concentration because of their popularity. We tested our estimator with several benchmarks and the results show that we receive accurate area and timing estimates efficiently.