Practical scan test generation and application for embedded FIFOs

This paper describes a method for testing non-scanned embedded latch-based FIFOs on an otherwise full-scan chip by using the scan registers that surround the FIFO and sharing the test application time with the other ASIC scan tests. The technique of excising the FIFOs from the ASIC to allow separate and effective test generation for each is explained, as is the process used to merge the two tests back together for efficient test application. Results are presented for three example ASICs which indicate that the method is both efficient and thorough.