Testability evaluation of sequential designs incorporating the multi-mode scannable memory element

The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with a full scan capability to support custom test vectors, diagnosis, and design debugging. A key feature is the ability to support pseudorandom at-speed delay testing of the functional circuit paths without imposing any performance penalty on the design beyond that for traditional scan. This paper presents a CMOS design for the MSME, and investigates benchmark circuits designed with this memory element. The results show that very high stuck-at and transition delay test coverage can be achieved for most cases using the pseudorandom self-test mode alone. Evaluation of layouts indicates low to moderate area overhead.