A full-rate 40 Gb/s clock and data recovery with resonator-based frequency-doubling mechanism in 0.13-μm CMOS

The paper presents a CMOS clock and data recovery (CDR) circuit for a full-rate 40 Gb/s optical receiver, and the proposed CDR adopts a mixer-based phase detector (MBPD). The MBPD approach offers several advantages such as capability to operate high frequencies, and a linear relationship between the phase difference and the output current. However, an MBPD requires a frequency-doubling mechanism (FDM) preceding the mixer, and the FDM becomes the bottleneck for high speed operations. Existing circuits implement the FDM with XOR gates and delay cells, which is limited for a low frequency range. The FDM for the proposed CDR is based on an LC-resonator, which doubles the clock frequency compared with competing CMOS CDRs. The proposed CDR is implemented in 0.13-μm CMOS technology. It achieves a peak-to-peak clock jitter of 0.755 ps for a 40 Gb/s pseudo-random binary sequence of (2
³¹
-1) bits and dissipates 75 mW.