A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement

This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to relax the DAC settling requirement. In addition, an addition-only digital error correction technique is utilized to convert the non-binary codes into binary ones. A 10-bit SAR ADC is designed in a 28-nm FDSOI CMOS technology. The ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 59.69 dB at the Nyquist input frequency, while consuming 1.53 mW from a 1.0 V power supply at 400 MS/s. The resulting figure-of-merit (FOM) is 4.86 fJ/conv.-step.