A 1 Gpps asynchronous logic OOK IR-UWB transmitter based on master-slave PLL synthesis

This paper presents an asynchronous logic high data rate IR-UWB transmitter operating with a single 31.25 MHz reference that robustly synthesizes 1 GHz rate pulses to enable sub-meter range neural data transmission. It is designed for a low power CMOS-based implantable electrode array and operates with a master-slave PLL cascade and a simple static CMOS logic combining. The master PLL consumes a simulated 1 mW power, and locking is based on the evolution of three non-overlapping feedback loops whose switching is controlled by a duty cycling window. The transmitter core enables OOK data transmission with a ~3.1 pJ/pulse energy budget, comprising master and slave PLL and antenna buffer contributions. The paper introduces the TX core architecture, details the master PLL operation and presents simulation results obtained in a 130 nm RFCMOS technology prior to measurement verification.