Analytic modeling of static noise margin considering DIBL and body bias effects

In this paper an analytic model of the inverter static noise margin (SNM) is presented. The drain-induced barrier lowering (DIBL) effects are considered in view of the fact that their influence becomes more critical in nanometer (below 90 nm) bulk CMOS nodes, as devices are dimensioned with minimum sizes and operate in sub-threshold region. The inclusion of body bias effect in the SNM model is proposed since the FD-SOI CMOS process allows the substrate voltage on a wide range, making it crucial trade-off exploitation involving speed and power consumption in low power applications. In addition, a fast approach for the estimation of the worst-case noise margin under the variability of the manufacturing process is proposed. The analytic and statistical expressions were verified by comparisons with extensive electrical simulation results obtained with a 28 nm FD-SOI CMOS process.