High speed pipelined 64-point FFT processor based on Radix-22 for wireless LAN

This Paper presents high Speed pipeline 64-point FFT processor based on Radix-2² for wireless LAN communication systems. This method uses Radix-2 butterfly structure and Radix-2² CFA algorithm. Radix-2 butterfly's complexity is very low and Radix-2² CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. An efficient VHDL code has been written, synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim PE Student Edition 10.4a. Also MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 158.96 MHz after the synthesis process and SQNR 37.02dB for 64 point.