The chamber memory effect induces P+ junction leakage and EEPROM tunneling oxide degradation

In middle of 1998, the failure modes of P+ junction leakage and tunneling oxide degradation on logic products (single poly, single metal 9 V LCD driver products) and EEPROM products (single poly, single metal 5 V EEPROM products) were found. From failure analysis, we found that a chamber memory effect was the root cause. In foundry fabs, an oxide etcher sometimes must run different recipes to meet manufacturing requirements, e.g. contact, spacer and via etching recipes. Due to these mixed recipes running in the same oxide etch chamber, interactive effects of different recipes occur. In this case, a special BiCMOS via etch recipe (recipe A) affected the spacer etch recipe of logic and EEPROM processes. We found that if logic and EEPROM products ran the spacer etch behind the via recipe A in the same chamber, then higher P+ junction leakage can happen on logic and EEPROM products and tunneling oxide degradation can happen on EEPROM products. Our failure analysis showed that CF/sub 4/ gas played a major role in inducing chamber memory effects in via recipe A. Due to process requirements, via recipe A uses CF/sub 4/ only to etch IMD layers to enlarge via size for RC via value reduction. The via etch recipe A with only CF/sub 4/ gas could change the chamber conditions, similar to the chamber dry cleaning recipe in equipment PM. Free F radicals remained in chamber after recipe A was run. When subsequent logic and EEPROM product lots ran spacer etching, contaminant atoms were released from the chamber wall and re-deposited on Si surfaces at source/drain and EEPROM floating gate edge areas. This paper details the failure analysis process.