Effects of stress concentration on metal voiding during dielectric deposition

The reliability of back end of line (BEOL) metallization for interconnection of semiconductor devices is extremely important. It is necessary that the metal lines be void free to meet electromigration requirements for advanced semiconductor devices. The reactive ion etching (RIE) of Al-Cu (0.5%) metallization is suspected to cause metal voids. Our systematic study of metal voids reveals the role of stress and stress concentration in void formation during dielectric material deposition after interconnect patterning by RIE. The stress simulation confirms the stress concentration at certain points on metal lines that lead to void formation. The role of side-wall (SW) angles of metal lines formed by RIE in stress concentration has been investigated. The effect of different dielectric materials such as spin on glass (SOG) and chemical vapor deposited (CVD) tetraethyl oxysilane (TEOS) on void formation has also been studied.