Digital PLL design challenges for cellular RFICs

Digital PLL design challenges for cellular RFICs are presented. 5 digital PLLs are integrated in 28nm CMOS to support 3-Rx carrier aggregation (CA)/2-TxCA of FD-LTE/TD-LTE, GSM/EDGE, WCDMA/HSPA, and TD-SCDMA. The 400 kHz fractional spur of GSM/EDGE Tx LO is < −68 dBc for all channels. The integrated phase noise (IPN) degradation due to DCO-to-DCO coupling is < 0.5 dB even if two fractional PLLs are locked at same frequency.