Computer based modeling for predicting reliability of flip-chip components on printed circuit boards

Flip-chip technology, developed in the early 1960s, is being positioned as a key joining technology to achieve high-density low profile mounting of electronic components on printed circuit boards (PCBs). At present, a process route that enables integration of this technology into standard assembly processes does not exist. Therefore, flip-chip technology is currently restricted to low volume products. This paper describes modelling technology and its use in providing data governing both the assembly and subsequent reliability of flip-chip components. Stress predictions, using finite element calculations, have been undertaken by a number of groups to predict thermal stress and fatigue in solder joints for a number of components. These simulations generally assume that the solder material starts in a stress free state, where defects arising during the reflow process are avoided. At present, very little has been published on the formation of solder joints during the reflow process, where integrated models for solidification and stress are required. This paper provides details on these models and how they are being used to identify suitable stand-off heights and process conditions for small pitch flip-chip assembly on FR4 substrates.