Reconfigurable pipelines in VLIW execution units

The basic question addressed was whether the greater hardware utilization offered by reconfigurable functional units could compensate for a reduction in clock rate. That is, would the average number of clock cycles per instruction improve sufficiently to compensate for a slower clock rate to yield a net improvement in performance? The architecture limited the number of execution units because of constraints external to the execution units. An example of such a constraint would be limited efficient access to a common register file. Under these constraints, inefficient matching of program needs with hardware capabilities limits performance because of hardware idle cycles. The work found very limited conditions that can yield performance improvement using reconfigurable pipelines when compared with static pipelines. Greater promise was found with instruction set enhancements made possible by the reconfigurable pipelines.