Asserting causal properties in High Level Synthesis

ICs are subject to many causes of malfunction such as aging or aggressive environment, while avoiding unwanted behavior of critical applications is a key issue. Monitoring is a cornerstone of safety policies, as it supports triggering counter measures on demand. High Level Synthesis (HLS) allows to easily implement applications in hardware, and some HLS compliant solutions have been reported. These solutions monitor applications through asserting properties to variables. This paper extends this approach by proposing causal assertions, dedicated to monitoring the evolution of variables over time. Results demonstrate significant gains in term of reactivity and error coverage rate, while keeping the overhead low.