Low-cost vertical coupling schemes for optical I/Os and 3D integration in CMOS photonic integrated circuits

Grating coupler structures have attracted prominent research and development efforts to address off-chip, vertical light coupling for wafer-level test and complex optical assemblies. In fact, three-dimensional (3D) integration is introduced as the key enabling technology for low footprint, high frequency and low loss silicon photonic and opto-electronic integrated circuits. Towards this direction, low-cost and CMOS compatible fabrication processes are required for the cost-effective mass-manufacturing of silicon photonic devices by CMOS foundries. This paper presents the recent research outcomes on effective perfectly normal grating couplers designed and fabricated on 340 nm thick silicon-on-insulator (SOI) following low cost methodologies that comply with CMOS fabrication processes while minimizing lithography and etching steps.