Layout-Based Test Coverage Verification for High-Reliability Devices

Test quality is critical to eliminate test escapes and to achieve high-reliability large-scale integrated (LSI) devices. This paper proposes a new concept called “physical test coverage” to verify test coverage based on the physical layout of LSI circuits. The physical test coverage is calculated as the ratio between the critical area of all wires in a device and that of wires undetected by LSI tests. From the critical area of undetected wires and the defect density of a manufacturing line, the risk of test escapes can be predicted. To effectively develop LSI tests that can minimize the number of test patterns, undetected wires are prioritized by the critical area related to each wire. Even when the conventional “logical” test coverage is high enough to satisfy the coverage criterion, some LSI devices investigated in this paper showed low physical test coverage depending on the physical layout of the LSI circuit. The concept of physical coverage was applied in the test development of some LSI products, and the test quality was substantially improved, such that 90% of test escapes of a device were eliminated.