VHDL-based modeling of a hard real-time task processor

Hard real-time systems are increasingly used in various areas of human activities. They are often implemented by means of specialized solutions, mostly of a suitable hardware/software combination. A frequently adopted approach to the realization of the hardware part is based on ASIC, usually a "general purpose" processor which operates according to real-time constraints. This work describes the modeling of a processor for the hard real-time domain, which is structured as a collection of "task processors" being supervised by another one dedicated to the "kernel" functions. Specifically, the behavior of the task processors is modeled using VHDL and subsequently simulated and tested. The paper also addresses the modeling process by (i) evaluating available CAD tools, and (ii) determining the detailed requirements on the behavior of the task processor. The outcome of these steps influenced the modeling process as the tools used were of restricted functionality, and processor behavior enforced a particular decomposition, respectively. Because of a restricted VHDL subset available, it was necessary to model the task processor on the lowest level of behavioral abstraction. The task processor has been tested against selected test programs written in a corresponding assembly language specially developed for this purpose.