Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFETbased system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R
_{on_sp}
) ratio (BV
²
/R
_{on_sp}
). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV
²
/R
_{on_sp}
for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.