A −242-dB FOM and −71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique

This work presents an ultra-low jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). Despite a high multiplication factor (i.e., 64), the proposed SLF-PLL concurrently achieved ultra-low jitter and low reference spur. From the prototype that was fabricated using a 65-nm CMOS process, the RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively.