Insights Into the Power-Off and Power-On Transient Performance of Power-Rail ESD Clamp Circuits

The power-off and power-on transient performance of power-rail electrostatic discharge (ESD) clamp circuits is investigated in this paper. In order to serve this purpose, the transient performance of a timed shutoff power-rail ESD clamp circuit in a 65-nm CMOS process is characterized by a three-terminal test method. Based on the characterization results, several insights are summarized: it is found that the bigFET response time of the investigated circuit is dependent on the pulse peak voltage. Besides, the resistor-capacitor network is verified to be a slew-rate detector instead of a rise-time detector. Moreover, the different bigFET response mechanisms under various power-on disturbances are clarified. In addition, the validity of these insights for other designs is also discussed in this paper.