Wafer Level Integration of 3-D Heat Sinks in Power ICs

In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-i-n diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process.