A highly linear 4-bit DAC with 1 GHz sampling rate implemented in 28 nm FD-SOI process

This paper presents the design of capacitive divider based 4-bit digital-to-analog converter to be used as sub-DAC in a novel concept sub-ranging ADC. The major goal of this project is not the DAC resolution itself but its linearity. The integral and differential nonlinearity of the DAC have to be as low as in case of 14-bit converter. It turns out there are two factors limiting the DAC linearity: the capacitors sensitivity to process variations and the leakage current of the transistors used in the switch. The DAC has been implemented in 28 nm FD-SOI process.