Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model With Parasitics

In this paper, we analyze stability metrics [e.g., read, write noise margins (WNM), and access time], geometrical variability, and layout area optimization of silicon nanowire field effect transistor (SiNW FET) based 6T SRAM with multiwire sizing technique. The SRAM cell analyzed in this paper is based on the TCAD and experimentally verified SiNW FET Verilog-A compact model with parasitics. The different NW SRAM design configurations (e.g., C_111, C_123, etc., where C_111 denotes the number of wires in pull-up, access, and pull-down transistors, respectively) are investigated. The read static noise margin and read access time (RAT) are improved up to ~38% and ~18% with little pay of WNM by ~9% (↓), write access time (WAT) ~33% (↑) in C_112 configuration compared to C_111. Other configuration such as C_113 possess more improvements upto ~55%, ~20% in RNM, RAT with WNM (↓~21%), and WAT (~44%↑) compare to C 111 at the expense of more layout area. Finally, the impact of geometrical variability including length, radius, and oxide thickness on the read and write stability using N-curve is examined. It is found that the static read and write stability is less susceptible to variability at nominal supply voltage. However, it is very sensitive to the voltage scaling in which read (write) voltage margin varies upto ~2-3% (~2.5-4.5%) and read (write) current margin varies upto ~18% (~35%) depending upon the design configurations. Among all design configurations, C_112 is the better configuration for considering overall performances such as write stability, speed, layout area, and variability tolerance.