Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing

A 19.2 Gb/s per lane link with IBM's latest POWER8 processor module has been analyzed. This paper presents the overview of the high-speed link design from the signal integrity point of view. Design approaches in package and printed circuit board (PCB) to support the target data-rate have been discussed. The end-to-end communication bus is modeled from extracted post-route design with a 3-D full-wave extractor and has been simulated with IO properties at system level. Bath-tub curves are generated from data gathered in functioning systems running this 19.2 Gb/s link to confirm the operation of the link meets the required bit-error-rate criteria as the modeling and simulation predicted.