Reliability Evaluations on 3D IC Package beyond JEDEC

3DIC technology has enabled scaling beyond the Moore's Law to achieve higher transistor count, increased functionality and superior performance. Additionally, this technology allows integrating heterogeneous components such as Processor, FPGA, GPU, Memory, Serdes, etc. on the same interposer die enabling faster computing through reduced latency. The yields on the 3DIC technology have matured and are equivalent monolithic flip chip products. All of the above has made 3DIC technology the key driver for some of the high end computing applications such as Data centers. Any technology is viable only if the end product is reliable and manufacturable with high yields. Understanding the reliability margin of 3D IC package is essential for making them commercially successful. Standard product qualification tests use JEDEC test standards for qualifying the product before ramping into mass production. This might be enough for standard flip chip and wirebond technologies, which have been deployed in the field for many years and the failure modes and acceleration factors are well understood. However, in 3D IC technology, both the assembly process and the assembly materials are new and evolving. Small variations in the process parameters or variations in material concentrations could have significant impact on the reliability. A comprehensive reliability study including component, board and system level is therefore very essential to capture interactions due to process and material variations and material interactions. This paper will compare the results of an extended reliability test evaluation for 3D IC package. This extended reliability study utilized a component level test vehicle, functional board level test vehicle and power cycling test vehicle for comprehensive understanding of the reliability margin. The component level tests followed the standard qualification practice. The functional reliability test set up used specially designed board to test the system level reliability. The functional test vehicle much like a probe card provides access to active circuitry in the stacked silicon, ubumps and C4 bumps while being mounted on the board. This enables replicating the component level tests on a board level. The power cycling tests were performed by utilizing the same functional board test vehicle and special software patterns were implemented to perform power cycling. Special software patterns were designed to heat the device and control the fan for cooling. This study has compared the extended reliability of multiple 3DIC devices with interposer sizes starting from 24mm and extending upto 36mm which is beyond the size of the standard reticle. Also, this study has compared the extended reliability of 3D IC package with eutectic and copper pillar C4 bump. The reliability tests have been conducted on multiple lots over time as an extended reliability monitor to capture process variations. The extended tests have been critical in finding process and material defects critical for improving the overall reliability margin of the 3D IC device.