Board Level Reliability Optimization for 3D IC Packages with Extra Large Interposer

3D IC packages with stacked silicon interconnects (SSI) have many performance advantages over conventional flip chip packages. Using SSI, various die using the same or different technology can be connected to each other with the use of an interposer. The interposer allows a large number of die-to-die connections, enabling higher interconnect bandwidth, lower power consumption, and lower I/O latency. With the demand for higher integration, extra-large interposer packages were developed with die sizes greater than the reticle size. Our study evaluated the board level reliability of 55 mm 3D IC packages with interposers as large as 45 mm. The packages were assembled with multiple 20 nm Cu/ELK (extreme low-k) die mounted on through-silicon via (TSV) interposers. With extremely large interposer packages, the assembly process and materials must be optimized to reduce the package stress and warpage that can lead to package or solder joint failures. The effect of different factors such as board pad design and assembly on board level reliability was evaluated on 55 mm 3D IC packages with an extremely large TSV interposer assembled with organic substrates. Lid construction (1-piece vs. 2-piece lid) and substrate material properties that can affect package warpage and solder joint reliability were also assessed. Our study results indicated the assembly materials and package construction have significant impact on the board level reliability.