3D Packaging Challenges for High-End Applications

In this paper, the processing and integration challenges addressed during the 3D packaging of a ~400 mm2 logic die are presented and discussed. The logic die was fabricated using GLOBALFOUNDRIES' 14-nm technology with 5x55 μm Through Silicon Vias (TSVs) integrated in the process as a via middle flow [1]. Fully fabricated test wafers were thinned down to 50 μm, using Amkor Technology's Middle End of Line (MEOL) process and TSVs were revealed [2]. Device performance was measured before and after thinning to validate no shift in performance. Wafers were diced and assembly performed on a multilayer laminate using flip chip bonding with a mass reflow process for both bottom and top die. Warpage control ensured that 100% wetting was achieved. Two top dies (mechanical High Bandwidth Memory (HBM) dies) were assembled on this stack using micropillars. A novel machined lid was designed to fit the package and improve thermal performance of the package. Simulation data of the lid design showing the thermal improvement is presented. Finally, the packages were tested after three-dimensional (3D) assembly, and the T0 assembly yield data is presented.