A high-current InP-channel triple heterojunction tunnel transistor design

VLSI devices are constrained by CF
dd
²
/2 power dissipation. Low power dissipation requires low V
dd
, yet reducing V
dd
increases I
off
. Tunnel FETs (TFETs) have steep subthreshold swings (S.S.) and can operate at low V
dd
, yet their I
on
is limited by low tunneling probability. This low I
on
results in large CV
dd
/I delay and slow logic operation. For greatly increased Ion, we had proposed a triple-heterojunction (3HJ) TFET design incorporating source and channel heterojunctions (HJ) [1, 2]. The designs of [1, 2] have an InAlAsSb channel, yet no low-trap-density dielectric interfaces to InAlAsSb have been reported. In contrast, low-trap-density dielectric interfaces have been demonstrated to InAs, InGaAs, and InP [3, 4, 5]. Here we propose an InGaAs/GaAsSb/InAs/InP 3HJ TFET design, with growth lattice-matched to InP. The gated channel surface is InAs and InP, and thus can have low trap density. The p-type side of the tunnel junction is GaAsSb, instead of strained GaSb [6], as compressive strain increases the hole transport effective mass, reducing the tunneling probability. In ballistic simulations, with I
off
= 10
³
μA/μm and V
dd
=0.3V, I
on
is an extremely high 540μA/μm. Even when simulated assuming incoherent quantum transport, with acoustic and optical phonon scattering modelled, I
on
remains very high at 250μA/μm.