A 16GS/s 6-bit current-steering DAC with TI topology in 40nm CMOS

A 6-bit pseudo segmented current-steering digital-to-analog converter (DAC) designed in 40nm low-leakage (LL) CMOS process is presented. The DAC employs 4× time-interleaved (TI) topology which enables sampling rates up to 16GS/s with relatively low clock frequency. A design-for-test on-chip memory with 6bits1-k bytes/bit is programmed with strictly costumed data sequence and read out at 1Gb/s rate, independently. The DAC achieves 5.54-bit effective number of bit (ENOB) and 42.33dBc spurious free dynamic range (SFDR) at Nyquist frequency, respectively. Simulation results show the DAC consumes less than 230mW power dissipation from 1.1V supply.