Detailed placement in advanced technology nodes: A survey

With the continued scaling to emerging technology nodes, modern circuit designs in nanometer era introduce many strict or even unprecedented design constraints and challenges. On one hand, conventional 193i wavelength lithography has pushed to its resolution limit, and the gap between manufacturing capability and design expectation becomes more critical. On the other hand, new metal layer (e.g. middle-of-line layers) as well as new device layer rules become more complex and restricted. We argue that detailed placement is the appropriate stage to consider the emerging manufacturing and design rule constraints. In this paper, we discuss sophisticated design constraints and challenges in emerging technology nodes, and survey the state-of-the-art detailed placement solutions and methodologies to overcome these challenges.