Embedded SRAM designs for enhancing performance, power and area (PPA) in 16 nm FinFET technology

We demonstrate SRAM circuit design techniques for enhancing performance, power and area (PPA) in 16 nm FinFET technology. The wordline overdrive (WLOD) assist circuitries with dual power rail are introduced for not only 6T single-port SRAM bitcell but also for 8T dual-port bitcell, improving minimum operating voltage (Vmin) by enhancing write-abilities. The read access times are also improved by WLOD. We also implement a high-density 2-port SRAM using 6T bitcell with double pumping scheme, enabling about 2× higher density than conventional 8T bitcell design. The resume standby circuit, which is adoptively controlled the bias of VSS source lines in cell arrays, is introduced for reducing leakage power. The measured silicon data show that the Vmin, read access time, and standby power are improved by up to 45%, 50%, and 80%, respectively.