A study of accurate extraction of ESD parasitic capacitance

On-chip electrostatic discharge (ESD) protection are required for all ICs. Unfortunately, ESD-induced parasitic capacitance (C
_ESD
) will seriously affect performance of high-speed and RF ICs. Careful design balance of ESD protection level and minimizing ESD-induced circuit performance degradation has become a major design challenge for high-speed and RF ICs. This paper presents a comprehensive study on accurate extraction of parasitic capacitance for on-chip ESD structures. A new simple and accurate CESD-extraction technique is presented for practical IC designs, which was validated using RF, ring oscillator and I/O buffer circuit blocks implemented in a foundry 28nm CMOS technology.