Fabrication and optimization of a high speed deep-trench super-junction MOSFET with improved EMI performance

Super-junction (SJ) devices have the advantages of low Drain-Source on-state Resistance (Rdson) and high switching speed. Although it is a Si-based device, it breaks through the classical law of Si power devices. This kind of non-classical MOSFET structure even realizes high performance comparable to III-V devices. However, Electromagnetic Interference (EMI) problem becomes an issue when the SJ devices switch too fast, especially for the deep-trench SJ-MOSFET. In this work, we studied the reason of inferior EMI performance of deep-trench SJ-MOSFET. It is found that there is an abrupt change in gate-drain capacitance (Cgd) when the p/n pillars close to full depletion. Based on this observation, an optimized deep-trench SJ-MOSFET is designed and fabricated in order to improve its abrupt change in capacitance. The abrupt change in gate-drain capacitance with the increasing drain voltage is smoothed in the capacitance measurement. As a result, a larger EMI margin is obtained in the application circuit using the proposed deep-trench SJ-MOSFET devices.